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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 16c. Temperature Hysteresis Limit
Register Bits
Table 16e. APC Hysteresis Limit
Register Bits
TxHIST[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FUNCTION
1 LSB (1/8 of a degree). I.e., no hysteresis
2 LSBs (1/4 of a degree)
3 LSBs (3/8 of a degree)
4 LSBs (1/2 of a degree)
5 LSBs (5/8 of a degree)
6 LSBs (3/4 of a degree)
7 LSBs (7/8 of a degree)
8 LSBs (1 degree)
9 LSBs (1 1/8 of a degree)
10 LSBs (1 1/4 of a degree)
11 LSBs (1 3/8 of a degree)
12 LSBs (1 1/2 of a degree)
13 LSBs (1 5/8 of a degree)
14 LSBs (1 3/4 of a degree)
15 LSBs (1 7/8 of a degree)
16 LSBs (2 degrees)
AxHIST[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FUNCTION
1 LSB. I.e., no hysteresis
2 LSBs
3 LSBs
4 LSBs
5 LSBs
6 LSBs
7 LSBs
8 LSBs
9 LSBs
10 LSBs
11 LSBs
12 LSBs
13 LSBs
14 LSBs
15 LSBs
16 LSBs
Table 16d. APC Difference Limiter for
Averaging
A_LIMIT[2:0]
000
001
010
011
100
101
110
111
FUNCTION
No limiting is applied
Difference is limited to 1 LSB (1/8 of a degree)
Difference is limited to 3 LSBs (3/8 of a degree)
Difference is limited to 7 LSBs (7/8 of a degree)
Difference is limited to 15 LSBs (1 7/8 degrees)
Difference is limited to 31 LSBs (3 7/8 degrees)
Difference is limited to 63 LSBs (7 7/8 degrees)
Difference is limited to 127 LSBs (15 7/8
degrees)
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